(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to integrate a gate insulator layer, comprised of a high dielectric constant (high k), material, into a CMOS device process sequence.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed device performance, as well as processing costs, to be reduced. The use of sub-micron features has resulted in reductions in performance degrading parasitic capacitances, while a greater amount of smaller semiconductor chips, comprised with sub-micron features, can now be obtained from a specific size substrate, thus reducing the processing cost for a specific semiconductor chip. The continuous scaling down of device dimensions necessitates the use of thinner gate insulator layers, and as the thickness of silicon dioxide layers used as a gate insulator layer decreases, integrity and leakage concerns, not present for gate insulator layers comprised of thicker silicon dioxide layers, become evident. The use of high k dielectric layers as gate insulator layers allow thicker layers to be used, with the thicker, high k dielectric layer supplying capacitances equal to thinner silicon oxide layers, or with the high k dielectric layer having an equivalent oxide thickness (EOT), equal to the thinner silicon dioxide counterpart layer. Therefore the use of high k dielectric layers, for gate insulator layer, will offer reduced leakage when compared to the thicker silicon dioxide gate insulator counterparts.
Metal oxide layers, such as aluminum oxide (Al2O3), zirconium oxide (ZrO2), and hafnium oxide (HfO2), are examples of high k dielectric layers, attractive as gate insulator layers for sub-micron devices, however the thermal stability of the metal oxide layers can be a problem when a gate metal insulator is formed prior to subsequent processing steps such as source/drain activation anneals, and metal silicide formation. The temperatures reached during these procedures can result in crystallization of the high k, metal oxide layer, resulting in undesirable gate leakage or shorts. This invention will describe a novel process procedure, and device structure, in which a high k, metal oxide layer is used as the device gate insulator layer, however formed and defined after high temperature anneals, and silicide formation procedures. Prior art, such as Wu, in U.S. Pat. No. 5,972,762, as well as Cha, in U.S. Pat. No. 5,970,329, describe methods of forming recessed elements in metal oxide semiconductor field effect (MOSFET), devices, however these prior arts do not describe the novel device process sequence, and novel process structure, illustrated in this present invention in which a device gate insulator layer, comprised of a high k, metal oxide layer, is integrated into a CMOS device process sequence after high temperature processes have been completed.
It is an object of this invention to fabricate a complimentary metal oxide semiconductor (CMOS) device featuring a high k dielectric layer for use as a gate insulator layer.
It is another object of this invention to integrate a high k, metal oxide, gate layer, into a CMOS fabrication sequence, after high temperature source/drain anneals, and high temperature metal silicide layer formation procedures, have been performed.
It is still another object of this invention to form the high k, metal oxide gate layer in a space surrounded by lightly doped source/drain (LDD), silicon spacers, wherein the space was created by removal of a silicon nitride masking shape, which in turn is used to define recessed source/drain regions as well as to define word lines.
In accordance with the present invention a method of integrating the formation of a high k, gate insulator layer into a CMOS fabrication procedure, at a stage of the CMOS fabrication procedure after which high temperature procedures have already been performed, is described. After formation of an N well, and of a P well region, for accommodation of P channel (PMOS), and N channel (NMOS), devices, a silicon nitride shape is formed on the surface of the well regions and used as a mask to selectively remove, and recess, unprotected silicon regions. Heavily doped P type, and N type, source/drain regions are then formed in the recessed portions in the P and N well regions, via ion implantation and annealing procedures, used to activate the implanted ions. Deposition of in situ doped polysilicon layers, and dry etching procedures, result in the formation of P type, and N type, lightly doped source/drain (LDD), spacers, on the sides of the silicon nitride shapes, as well as on the sides of the non-recessed silicon shapes, underlying the silicon nitride masking shapes. Metal silicide regions are next formed in portions of both the P type, and N type heavily doped source/drain region, via formation of a metal shape followed by anneal procedure. After formation of a planarizing insulator layer, the silicon nitride shapes are removed, exposing the surrounding LDD spacers, and exposing underlying non-recessed silicon, located between he heavily doped source/drain regions. A high k, metal oxide layer is deposited, filling the space vacated by the silicon nitride shape, followed by deposition of a conductive layer. Patterning procedures are used to define a conductive gate structure, overlying the high k, metal oxide gate insulator layer. Deposition of, and planarization of, an overlying insulator layer, is followed by definition of contact openings in the insulator layer, exposing portions of top surfaces of the recessed, highly doped source/drain regions, as well as portions of the top surface of the conductive gate structures. Deposition of, and patterning of, a metal layer, results in creation of metal contact and interconnect structures located in the contact openings.